1. Field of the Invention
The present invention relates to a shift register and a device, such as a display or an image sensor, using the same.
2. Description of the Related Art
FIG. 14 is a circuit diagram which illustrates the internal circuitry of a stage F101 incorporated in a conventional exemplary shift register. The stage F101 includes an input terminal IN at which a signal Gixe2x88x921 output from a previous stage is input, an output terminal OUT at which a signal Gi is output to a subsequent stage, clock input terminals Ka and Kb at which clock signals xcfx86a and xcfx86b are input, respectively, and a ground terminal GND connected to a ground potential.
FIG. 15 is an overall view of the conventional exemplary shift register. The shift register is formed of a plurality of stages F101, F102, F103, and the like. The internal circuitry of the stages F102, F103, and the like is the same as that of the stage F101 shown in FIG. 14. The stages F101, F102, F103, and the like are connected to each other in the cascade configuration. For example, the output terminal OUT of the stage F101 is connected to the input terminal IN of the next stage F102. As above described, the stages F102, F103, and the like have the same circuitry as the stage F101, and the stages F101, F102, F103, and the like each have ground terminals GND which are connected to the ground potential via a ground line. As used herein, ground potential refers to the initial state level of the internal components of the stages F101, F102, F103, and the like. That is, in the initial state, a ground potential is output from the output terminal OUT of each of the stages F101, F102, F103, and the like.
However, the conventional shift register has the following problems; it requires a line, such as a ground line, which supplies the initial state level to each stage in the shift register, so that the number of lines in the shift register increases, leading to an increase in size of the area required for wiring.
Accordingly, it is an object of the present invention to provide a shift register having fewer lines to reduce the size of area required for wiring, and to provide a display using the shift register.
To this end, in one aspect of the present invention, a shift register has m stages which store one of two states, where m is an integer more than 1, each stage including clock input terminals at which n-phase clock signals are input, where n is an integer more than 1, and an input terminal, and an output terminal. The input terminal of one stage receives the signal delivered from an input terminal of the shift register or from the output terminal of the previous stage. The signal output at the output terminal of one stage is passed to the input terminal of the subsequent stage or to an output terminal of the shift register. Each stage receives an initial state level from one of the clock input terminals. The initial state level is used to initialize the state of each stage.
Since the initial state level is input from one of the clock input terminals, a line, such as a ground line, which supplies the initial state level is eliminated. Therefore, fewer lines are connected to the shift register, thereby reducing the size of area required for wiring.
Two- to four-phase clock signals would provide optimum number of clock signal lines, thereby reducing the size of area required for wiring.
Preferably, the stages in the shift register are divided into a plurality of groups, and the in-phase clock input terminals of the stages in each group are all connected to each other.
This allows the clock input terminals of the stages in each group to be integrated into one system, and each group is provided with a set of clock input terminals. Thus, the clock signal lines in the shift register may not extend across the shift register. Therefore, the length of the clock signal lines in the shift register may be reduced, thereby reducing a delay of the clock signals due to the line capacitance or the line resistance.
Preferably, each stage further includes a storage unit for storing one of two states, and an initializing unit for initializing the state stored by the storage unit to the initial state level input from one of the clock input terminals.
The initializing unit (a transistor in an illustrated embodiment) may be used to initialize one of the two states, i.e., HIGH level or LOW level, which is stored in the storage unit (a capacitor in the illustrated embodiment) to the initial state level (the ground potential in the illustrated embodiment) which is input from one of the clock input terminals. Thus, a line, such as a ground line, which supplies the initial state level is not necessary in order to initialize the state of each stage in the shift register.
Preferably, the initializing unit is an MIS transistor, and MIS transistors contained in each stage, including that MIS transistor, are of the same channel type.
All of the MIS transistors are of the same channel type, thereby making the production process simplified. The MIS transistors of the same channel type would be achieved using multiphase clock signals.
Preferably, the MIS transistors are made of a material containing amorphous silicon or polycrystalline silicon.
When a voltage is applied in the same direction to a MIS transistor made of a material containing amorphous silicon or polycrystalline silicon, the reliability of the MIS transistor may be reduced in general. According to the present invention, however, the initial state level is input to the MIS transistor, or the initializing unit, from one of the clock input terminals having a time-varying potential, rather than a line having a potential which is always fixed at the initial state level. Thus, the direction of the voltage applied to the MIS transistor varies over time, and is not fixed to the same direction. Accordingly, the reliability of the MIS transistor is improved.
The outputs of the stages in the shift register may correspond to scan signals of an active matrix circuit having switching elements formed at intersections between signal lines and scan lines. Preferably, MIS transistors contained in the active matrix circuit, and the MIS transistors contained in each of the stages in the shift register are of the same channel type, and are made of a material containing amorphous silicon or polycrystalline silicon.
Since the outputs of the stages in the shift register correspond to scan signals of the active matrix circuit, that is, a gate driver or a source driver of the active matrix circuit is formed of the shift register, fewer lines are required for the gate driver or the source driver. The size of area required for the lines in the gate driver or the source driver is therefore reduced.
Preferably, the shift register is formed together with the active matrix circuit on the same substrate.
Since the shift register and the active matrix circuit formed on the same substrate, the line extending between the shift register and the active matrix circuit can be shortened. The MIS transistors which are formed on the same substrate may be formed using the same production process, and the MIS transistors in the shift register and the active matrix circuit may be of the same channel type, and may be made of the same material.
In another aspect of the present invention, a display uses the shift register in accordance with the present invention as a gate driver and/or a source driver.
Fewer lines are required for a shift register used as a gate driver and/or a source driver, thereby reducing the size of area required for wiring. This results in a compact display having a smaller wiring area than a conventional display without any influence on display capabilities.